High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

这门课程是对高级综合（HLS）中的时序电路设计的介绍。本课程的目标是在不使用HDL（例如VHDL或Verilog）的任何帮助的情况下，仅使用C / C ++语言描述，调试和实现FPGA上的顺序逻辑电路。

它使用Xilinx HLS软件和硬件平台演示了真实的示例和应用程序。该课程主要使用Xilinx Vitis-HLS工具集来描述，模拟和综合高级设计描述为等效的HDL代码。该课程还介绍了如何在Vivado中使用集成逻辑分析器（ILA）IP在Basys3板上执行实时调试。

本课程是第一门从头开始构建HLS设计流程和技能以及数字逻辑电路概念的课程。在整个课程中，您将遵循几个描述HLS概念和技术的示例。本课程包含许多测验和练习，供您练习和掌握所建议的方法和方法。此外，本课程利用三个令人兴奋的项目将所有解释的概念放在一起，以设计真实的电路和硬件控制器。

本课程是有关HLS的系列课程中的第二门课程，有关HLS的主题是在目标FPGA上设计硬件模块和加速算法。本课程着重于顺序电路，而第一门课程说明如何在HLS中描述组合电路。该系列的其他课程将介绍如何在设计高级逻辑电路，算法加速和混合CPU + FPGA异构系统中使用HLS。

MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 102 lectures (9h 28m) | Size: 7.02 GB
Logic Design with Vitis-HLS

What you’ll learn:
Designing sequential logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing sequential logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado design suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing three exciting projects with HLS

Requirements
Understanding the basic concepts of C/C++ coding
“High-Level Synthesis for FPGA, Part 1 – Combinational Circuits” course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado toolsets

Description
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.

This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.

This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Who this course is for
Hardware engineers
Software engineers who are interested in FPGA
Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
Digital Logic enthusiasts