Advanced VHDL for Verification

高级VHDL进行验证的内容，包括TextIO，配置，泛型，记录，BFM，多维数组和访问类型。

高级VHDL课程包括高级RTL功能以及验证行为功能：

-VHDL配置

-VHDL阵列

-在VHDL中对内存建模，在RTL中创建推断的内存

-在VHDL中建模和推断FIFO

-VHDL信号层次结构

-VHDL泛型，记录和别名

-VHDL文件I / O和TextIO

-为仿真创建伪代码

-开发VHDL总线功能模型

MP4 | Video: h264, 1280×720 | Audio: AAC, 44100 Hz
Language: English | Size: 936 MB | Duration: 4h 25m

What you’ll learn
Advanced VHDL for verification, including TextIO, configurations, generics, records, BFM, multi-dimensional arrays, and access types.
Requirements
Experience in VHDL RTL design. Introduction to VHDL course completion recommended.
Description
The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :

– VHDL Configurations

– VHDL Arrays

– Modeling memories in VHDL, creating inferred memories in RTL

– Modeling and inferring FIFOs in VHDL

– VHDL Signal Hierarchy

– VHDL Generics , Records, and Alias

– VHDL File I/O , and TextIO

– Creating pseudo-code for simulations

– Developing VHDL Bus Functional Models

Who this course is for:
VHDL RTL or Verification engineers who want to use the VHDL language to improve verification.