HDL Designer是一个强大的基于 HDL 的环境，它提供了设计当今最复杂的 FPGA 和 ASIC 的新方法。HDL Designer 在全球范围内被各个工程师和工程团队用于创建、分析和管理这些令人惊叹的设备的设计。
HDL Designer 通过自动化许多流程和任务来加速项目的生产力和可预测性。自动规则检查、寄存器生成和文档以及强大的文本、表格和图形创建编辑器可以节省大量的工程时间，并可以最大限度地减少手动引入的错误。整个项目的工具集成和版本管理有助于保持团队、工具和设计流程的结构化，但仍然足够灵活，通过 API 来增强现有的设计流程。通过这种自动化和项目管理，项目和由此产生的芯片的整体质量得到提高，项目风险大大降低。
通过使用 HDL Designer，可以通过这种自动化立即认识到节约和成本避免，并将通过更好的设计重用、编码的一致性和改进的文档在未来的项目中继续进行。对于安全和关键任务项目，HDL Designer 的设计检查、版本管理、寄存器生成和文档支持遵守法规遵从性要求，例如 DO-254 和 ISO 26262。
Mentor Graphics HDL Designer 工具套件，为客户带来生产力更高的设计输入、分析与管理功能，包括更强大的联机资料表格，无论设计复杂性如何，都能迅速建立高品质且结构良好的硬件描述语言。HDL Designer Series可协助工程师迅速输入和分析复杂的ASIC、FPGA和系统单芯片设计，让客户新产品于更短时间内上市。
Mentor Graphics公司HDL Designer Series行销总监Valerie Rachko表示，不管设计工程师采用何种硬描述语言设计方法，HDL Designer Series工具套件都为他们提供一套完整作业环境，使他们能轻易完成硬件描述语言设计、分析和管理。实际应用结果证明，包括Interface-Based Design™在内的多项特色让复杂线路描述更简单；为进一步满足工程师的设计需求，新版本还加强了文件记录、显示、除错与设计管理功能。
以界面为基础的IBD设计方法让复杂设计的线路描述更简单为了让线路设计更简单，以界面为基础的Interface-Based Design（IBD™）设计方法会用观看方便的精简表格来显示线路结构，这个表格编辑环境允许设计工程师迅速指定信号线路，然后产生对应的VHDL或Verilog结构描述，使用者甚至能以功能方块图的形式来观看IBD描述资料。
The software developer Mentor Graphics, is pleased to announce the availability of HDL Designer Series (HDS) 2019.4 is a powerful HDL-based environment used by individual engineers and engineering teams worldwide to analyze, create and manage complex FPGA and ASIC designs.
What’s New in HDL Designer Series 2019.4
Summary
SVAssistant
— High Level Block Diagram Visualization
— Visualizer Integration
— Multiple Simulation Configuration
— SystemVerilog performance improvements
– Scalability Mode
— SystemVerilog Find References
HDL Designer
— Simplified Vivado Integration Flow
DesignChecker
— General bug fixing
Quality
— >50 Defects & Enhancements Resolved
HDL Designer is a powerful HDL-based environment which delivers new approaches to design today’s most complex FPGAs and ASICs. HDL Designer is used worldwide by individual engineers and engineering teams to create, analyze and manage the design of these amazing devices.
HDL Designer accelerates the productivity and predictability of the project by automating many flows and tasks. Automated rule checking, register generation and documentation and the powerful text, tabular and graphical creation editors save incredible amounts of engineering time and can minimize manually introduced errors. Tool integration and version management of the entire project help keep the team, tools and design process structured, but is still flexible enough through an API to augment existing design flows. Through this automation and project management, the overall quality of the project and resulting chip is improved and project risk greatly reduced.
By using HDL Designer, savings and cost avoidance can be recognized immediately through this automation and will continue with future projects through better design reuse, consistency of coding and improved documentation. For safety- and mission-critical projects, HDL Designer’s design checking, version management, register generation and documentation support adherence to regulatory compliance mandates such as DO-254 and ISO 26262.
Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Product: Mentor Graphics HDL Designer Series (HDS)
Version: 2019.4 build 4
Supported Architectures: x64
Website Home Page : http://www.mentor.com
Languages Supported: english
System Requirements: PC *
Size: 809.3 mb
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