Cadence INNOVUS v18.10.000

全球电子设计创新的领导者 Cadence Design Systems, Inc. 公布了 INVUS 18.10.000 是更广泛的 Cadence 数字和签核套件的一部分，该套件为客户提供集成的全流程，提供可预测的设计收敛路径，并支持 Cadence 的智能系统设计策略，加速 SoC 设计的卓越。

Cadence Innovus 实施系统针对最具挑战性的设计以及最新的 FinFET 16 纳米、14 纳米、7 纳米和 5 纳米工艺进行了优化，可帮助您以更快的速度启动更早的设计。凭借在布局、优化、布线和时钟方面的独特新功能，Innovus 系统采用了一种架构，可考虑设计流程中的上游和下游步骤和影响。这种架构最大限度地减少了设计迭代，并提供了更快上市所需的运行时间。使用 Innovus 系统，您将能够以更低的风险构建集成的、差异化的系统。

Innovus 系统具有多种关键功能。其大规模并行架构可以处理大型设计并利用多核工作站上的多线程以及计算机网络上的分布式处理。

基于完善的 NanoRoute 引擎，具有轨道感知时序优化的下一代 slack 和功率驱动布线可在早期解决信号完整性问题并改善布线后相关性。Innovus 系统包括全流程多目标技术，这使得同时进行电气和物理优化成为可能。它还通过通用 UI 和用户命令与综合和签核工具共享可定制的流程。因此，您可以利用强大的报告和可视化功能，提高整个数字流程的设计效率和生产力。

随着单元数量和复杂性方面的块大小不断增加，需要在布局规划中定位的宏数量呈爆炸式增长。Innovus 系统提供混合宏和标准单元布局，可自动生成宏位置，从而将创建最佳布局规划的时间从几天缩短到几小时。

机器学习计算机科学的最新进展与数字实施流程非常相关。Innovus 系统结合了机器学习技术，可为最具挑战性的高性能模块提供最佳 PPA。设计人员可以完全控制机器学习培训，以确保根据他们的特定设计要求进行定制。

Cadence 的 Genus Synthesis 解决方案与 Innovus 系统紧密集成，可实现从 RTL 综合到实施的无缝转移。借助 GigaPlace 和 GigaOpt 引擎中用于 Genus 物理综合的共享布局和优化技术，这为高级节点设计融合提供了巨大优势。

随着最新 FinFET 工艺节点的电压降低，IR 和 EM 约束变得越来越重要。Innovus 系统包括全面的电源完整性感知布局、优化、时钟树和布线功能，以确保在实施过程中解决 IR 和 EM 违规问题，而不会影响最终 PPA。

Cadence 的 Tempus 时序签核解决方案、Quantus 提取解决方案和 Voltus IC 电源完整性解决方案与 Innovus 系统集成。通过这种集成，您可以在物理实现的早期阶段对寄生效应、时序、信号和电源完整性影响进行准确建模，并在这些电气指标上实现更快的收敛，从而实现更高效的设计收敛。

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled INNOVUS 18.10.000 is part of the broader Cadence digital and signoff suite, which provides customers with an integrated full flow, delivering a predictable path to design closure and also supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.

The Cadence Innovus Implementation System is optimized for the most challenging designs, as well as the latest FinFET 16nm, 14nm, 7nm, and 5nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus system, you’ll be equipped to build integrated, differentiated systems with less risk.

The Innovus system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.

Based on the well-established NanoRoute engine, next-generation slack and power-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity across the whole digital flow.

With block sizes growing in both cell count and complexity, the number of macros that need to be positioned in the floorplan is exploding. The Innovus system offers mixed-macro and standard-cell placement, which enables macro locations to be automatically generated, reducing the time to create an optimal floorplan from days to hours.

The latest advances in machine learning computer science are very relevant for digital implementation flows. The Innovus system incorporates machine learning technology to deliver the best PPA for the most challenging, high-performance blocks. The designer has complete control over the machine learning training, to ensure it is customized for their specific design requirements.

Cadence’s Genus Synthesis Solution is tightly integrated with the Innovus system, which enables a seamless move from RTL synthesis to implementation. With shared placement and optimization technology from the GigaPlace and GigaOpt engines for Genus physical synthesis, this offers a big benefit for advanced-node design convergence.

As voltage decreases in the latest FinFET process nodes, IR and EM constraints become increasingly important. The Innovus system includes comprehensive power integrity-aware placement, optimization, clock tree, and routing features to ensure IR and EM violations are addressed during implementation without impacting final PPA.

Cadence’s Tempus Timing Signoff Solution, Quantus Extraction Solution, and Voltus IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model parasitics, timing, signal, and power integrity effects at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in more efficient design closure.

Complete flow of innovus tool has been demonstrated in this video. Both command line and GUI mode have been covered in the same video. Important input files for this flow has also been discussed and how to create them has been explained.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence INNOVUS
Version: 18.10.000 Base release
Supported Architectures: x86
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: RHEL 5 (lnx86)
Size: 3.4 Gb