Siemens Mentor Calibre 2025.4

Mentor Calibre 2025.4（西门子 EDA Calibre 平台的一部分，原 Mentor Graphics 公司产品）是一款先进的集成电路物理验证和可制造性设计（DFM）套件，是业界签核设计规则检查（DRC）、逻辑验证（LVS）、寄生参数提取（PEX）和可靠性验证的黄金标准。此版本与正在进行的 2025.x 系列（继 2025.1 至 2025.3 之后）保持一致，重点在于增强性能、AI 驱动的生产力、左移验证策略以及对包括台积电 N3C、N2P 和 A16 工艺在内的先进节点的支持。Calibre 可在所有设计风格中提供可扩展、精确的验证，从而缩短流片周期，同时确保符合代工厂标准并优化良率。

Mentor Calibre 2025.4 (part of the Siemens EDA Calibre platform, formerly from Mentor Graphics) is the advanced IC physical verification and design-for-manufacturability (DFM) suite, serving as the industry gold standard for signoff DRC, LVS, parasitic extraction (PEX), and reliability verification. This release aligns with the ongoing 2025.x series (following 2025.1–2025.3), emphasizing enhanced performance, AI-driven productivity, shift-left verification strategies, and support for advanced nodes including TSMC N3C, N2P, and A16 processes. Calibre delivers scalable, accurate verification across all design styles, reducing tapeout cycles while ensuring foundry compliance and yield optimization.

Key Features of Calibre 2025.4

• Physical Verification (DRC): Comprehensive Calibre nmDRC with support for foundry-certified rules at advanced nodes; enhanced shift-left capabilities via Calibre nmDRC Recon for early, fast-feedback checking on incomplete designs.
• AI-Powered Enhancements: Integration of Calibre Vision AI for intelligent DRC violation clustering, prioritization, and debugging; improves efficiency by analyzing billions of errors, enabling faster full-chip signoff and collaboration through bookmarks and notes.
• Circuit Verification (LVS/PEX): Robust Calibre nmLVS and Calibre xACT/xACT3D for accurate layout-vs-schematic and parasitic extraction; second-generation Verilog-to-LVS delivers up to 4X faster runtimes and 92% reduced memory for large SoCs.
• Reliability and PERC: Calibre PERC for advanced ESD/latch-up checks and circuit reliability; AI-optimized resource distribution accelerates point-to-point resistance and current density analysis.
• 3D IC and Packaging Support: Extended capabilities with Calibre 3DSTACK for multi-die DRC/LVS, Calibre 3DStress for transistor-level thermo-mechanical stress analysis, and integration with TSMC 3DFabric technologies.
• DFM and Optimization: Calibre DesignEnhancer for automated via insertion, filler/DCAP placement, and power grid enhancements to reduce IR drop/EM issues.
• Performance and Scalability: Cloud-ready nmPlatform for high-throughput processing; improved multi-threading, memory efficiency, and support for latest OS versions (RHEL 9+ from 2025.2 onward).
• Interactive and Debug Tools: Calibre Interactive, RVE, and Auto-Waivers for streamlined debug, waiver management, and real-time in-design checking.