FPGA视频处理算法实现教程Video Processing with FPGA

This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

We have “Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm” on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

After Completing this course you will be able to:

Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

Migrating the OpenCV algorithm into XfOpenCV

MP4 | Video: h264, 1280×720 | Audio: AAC, 44100 Hz
Language: English | Size: 2.66 GB | Duration: 4h 21m

What you’ll learn
Implement different Computer Vision algorithm for Video Processing
Creating IP from the VIVADO High Level Synthesis
IP integration and configuration with Xilinx VIVADO
Xilinx SDK Application Development
Migrating the OpenCV algorithm on XfOpenCV
Simulating & Generating XfOpenCV codes in the VIVADO HLS
Integrating TPG, VDMA and Writing application for this blocks
Requirements
Basics of FPGA Design
High Level Synthesis Basics
PC with installed VIVADO, HLS and SDK [we will also show the steps for installation] Description

Who this course is for:
Electrical Engineering Enthusiast
Computer Science Enthusiast
FPGA Design Professional
Enthusiast of FPGA Design