Synthesizable SystemVerilog for an FPGA/RTL Engineer

FPGA 无处不在，它们在不同领域的存在日益增加。SystemVerilog 在验证域和 RTL 设计中起着主导作用。两者最好的部分是一旦您了解了 SystemVerilog，您就会自动理解 VHDL，然后可以使用这两个世界的功能来构建复杂的系统。本课程侧重于 Synthesizable SystemVerilog 结构，有助于构建可在 FPGA 硬件上测试的 RTL。该课程是通过分析大多数在该领域工作的公司所需的最常见技能来制定的。大多数概念都是通过考虑实际的实例来解释的，以帮助构建逻辑。

本课程说明了建模风格、阻塞和非阻塞分配、可综合 FSM、使用块和分布式内存资源构建内存、Vivado IP 集成器以及硬件调试技术（如 ILA 和 VIO）的使用。本课程使用 Xilinx Vivado 设计套件 2020 探索 FPGA 设计流程，并讨论实现所需性能的实施策略。详细说明了许多项目，以了解 Verilog 构造将真实外围设备连接到 FPGA 的用法。关于编写 Testebench 和 FPGA 架构的单独部分进一步加深了对 FPGA 内部资源和执行设计验证的步骤的理解。

MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz
Language: English | Size: 3.68 GB | Duration: 12h 5m

Using Xilinx Vivado Design Suite 2020

What you’ll learn
Fundamentals of SystemVerilog Programming that will help to ace RTL Engineer Job Interviews.
Understand Vivado Design Suite flow for Digital System Design.
Different Modelling Styles in Hardware Description Language.
How to use Xilinx IP’s and create Custom IP’s.
IP integrator Design flow of the Vivado.
Writing Verilog Testbenches.
Design of some real world projects such as : PMOD DA4 DAC interface, Function Generator, Small Processor Architecture, UART Interface, PWM, BIST for Development boards and many more.
Requirements
Fundamental of Digital Circuit will give an added advantages.
Description
FPGA’s are everywhere with their presence in the diverse set of the domain is increasing day by day. SystemVerilog plays the dominant role in the Verification Domain as well as RTL designing. The best part about both of them is once you know SystemVerilog you automatically understand the VHDL and then the capabilities of both worlds can be used to build complex systems. The course focus on the Synthesizable SystemVerilog constructs help to build RTL that can be tested on the FPGA Hardware. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite 2020 along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Who this course is for
VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.
Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ SystemVerilog Hardware Description Language
Anyone interested to start career in ASIC/ VLSI domain.