Cadence Virtuoso, Release Version IC6.1.8 Base

全球电子设计创新的领导者 Cadence Design Systems, Inc. 推出了 Virtuoso，发布版本 IC6.1.8 Base m 是一个基于系统的整体解决方案，提供了驱动 IC 和封装的仿真和 LVS-clean 布局的功能从一个单一的示意图。

Cadence Virtuoso 系统设计平台链接了两种世界一流的 Cadence 技术——定制 IC 设计和封装/PCB 设计/分析——创建了一种整体方法，可以自动化和简化多芯片异构系统的设计和验证流程。

利用 Virtuoso 原理图编辑器和 Virtuoso 模拟设计环境，它为 IC 和封装/系统级设计捕获、分析和验证提供了一个单一平台。此外，Virtuoso 系统设计平台提供与 Cadence SiP 级实施环境和 Clarity 3d Solver 的自动双向接口。

Virtuoso 系统设计平台使 IC 设计人员能够轻松地将系统级布局寄生参数包含在 IC 验证流程中，通过将封装/电路板布局连接数据与 IC 布局寄生电气模型相结合来节省时间。自动生成的“系统感知”原理图可以轻松用于创建最终电路级仿真的测试平台。Virtuoso 系统设计平台使整个流程自动化，消除了将系统级布局寄生模型集成回 IC 设计人员流程的高度手动且容易出错的过程。

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Virtuoso, Release Version IC6.1.8 Base m is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic.

CCRs Fixed in IC6.1.8 and/or ICADVM18.1 – Date: October 2018
Note: This CCR list represents those CCRs that were first addressed in the IC6.1.8 and/or ICADVM18.1 BASE releases.

The Cadence Virtuoso System Design Platform links two world-class Cadence technologies—custom IC design and package/PCB design/analysis—creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.

Leveraging the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, it provides a single platform for IC-and package/system-level design capture, analysis, and verification. In addition, the Virtuoso System Design Platform provides an automated bidirectional interface with the Cadence SiP-level implementation environment and Clarity 3d Solver.

The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The automatically generated “system-aware” schematic that results can then be easily used to create a testbench for final circuit-level simulation. The Virtuoso System Design Platform automates this entire flow, eliminating the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow.

This video shows the basic introduction to one of the most used IC design tools in the industry and academia – Cadence virtuoso. It also shows how to edit schematic design in cadence virtuoso.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Product: Cadence Virtuoso
Version: IC06.18.000 Base Release *
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 6.2 Gb