Sigrity 2021 软件，用于高频电路中的仿真和信号完整性。随着数字处理技术的进步，对更快处理的需求日益增长，Prdzashgrhayy 必然需要以更高的处理速度和更高的频率工作更快的电路。通过增加速度信号以准确加速安装在电路板上的线路上的信号 PCB 或电路板层压问题和新问题出现在 Field 的情况下，工程师将在高干扰、失真和噪声和信号完整性等事件频率导致受到威胁。
为了尽量减少这些威胁，补偿它们并提高高速电路的质量，需要分析和纠正措施，Allegro Sigrity 软件对我们来说很方便。该软件将技术与设计、编辑和布线 IC 以及 PCB 坐标 Cadence® Allegro® 相结合，可为用户提供预布局和后布局的高级分析。
该软件旨在检查初始阶段的各种场景，从而最大限度地减少精确设计和重新设计。本软件支持直接在Allego数据库的PCB和IC设计上读写。基于 SPICE 的精确模拟器以及用于 2d 和 3d 的内置求解器提取用户。该软件还对晶体管级输入和输出功能进行建模，包括对功耗感知 IBIS 5.0 的支持。
特性和应用 Allegro Sigrity： –
执行广泛的 SI 分析或信号完整性（Signal integrity） –
早期检测设计错误以增加早期阶段的
成功 – 可以快速准确地设置限制应用基本流程 – 提高
产品性能通过探索和空间解决方案
– 婴儿期替代拓扑的 评估 –
以参数 S 的形式生成拓扑的 S 参数和信号分析 –
旨在提高生产力的表估计干扰
– 在 PCB 设计和 IC 设计后直接在板上获得批准
-硅板上不同路径的多重评估和确认信号
Sigrity 2021 发布通过集成 3D 设计和 3D 分析来加速 PCB 设计周期：
互连建模技术： –
升级的互连建模技术解决了 PCB 和 IC 封装设计的最新趋势。随着信号速度攀升至 32Gbps 和更快，现在需要将 PCB 和连接器战略性地建模为一种结构。新的 Cadence® Sigrity™ 3D Workbench 包含在 Sigrity PowerSI 3D EM 提取选项 (3DEM) 中，允许用户导入机械结构，例如电缆和连接器，并将它们与 PCB 合并。这样，从电路板到连接器的关键 3D 结构可以作为一个结构进行建模和优化。PCB 的更新可以自动回注到 PCB 布局工具。
3D Workbench 提供：
-SI 和 PI 应用程序
– 熟悉的 3D 外观和感觉
– 能够导入机械结构
– 能够导入电气数据库并与机械结构合并
-3D 实体建模（参数化和全功能） –
模拟：
-Twisted成对接线（电缆） –
背板加连接器 –
连接器建模（HDMI、SATA 等） –
PCB 上的 SMA 连接器
刚柔结合：
业界首创的从单一布局数据库中提取的完整刚柔结合 PCB 可提供刚性和网状接地柔性电缆区域的精确互连建模。区域信息是从 Cadence Allegro® 技术 17.2 版自动导入的。
更快的 IC 封装建模： –
具有数千个凸点/焊球的设计的 IC 封装建模速度提高了 3 倍，内存消耗降低了 75%。
电源完整性更新： –
升级的电源完整性 (PI) 技术解决了 PCB 前后设计流程的新检查要求和新可用性要求。添加了许多增强功能，包括分层视图、快速搜索和过滤、比较树报告和工具提示。
Allegro PowerTree™ 技术：
– DC 分析技术已升级，支持与 Allegro 技术、HTML 框图增强和自动添加节点增强功能的集成。
Sigrity PowerDC™ 技术：
– 交流分析技术增加了一些额外的检查，现在查看加权交流电流并检查电压是否相等。新的批处理模式“项目”允许将这两个新工作流以及其他工作流设置为一组批处理检查。
Sigrity OptimizePI™ 技术： –
升级的信号完整性 (SI) 技术加快了验证内存接口、串行链路以及 PCB 上可能导致设计在实验室中失败的大量其他信号所需的时间。该技术现在具有工作流程和愿景，可用于快速执行电气规则检查，以发现阻抗变化和过度耦合。这些检查不需要模型，并且可以由信号完整性方面的专家和非专家运行。
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Description:
Sigrity 2021 software for simulation and signal integrity in high-frequency circuits. With the advancement of digital processing technology, the need for faster processing has grown increasingly, Prdzashgrhayy that necessarily needs to work faster circuits with higher processing speeds and higher frequencies are located. By increasing the speed signals for accurate speed up the signals on routes that are mounted on boards PCB or boards laminated issues and new problems arises in the case of Field, gripped engineers will be events such as interference, distortion and noise and signal integrity at high frequencies cause to be subject to threats.
To minimize these threats, compensate them and increase the quality of high-speed circuits, needs analysis and corrective actions that the software Allegro Sigrity it is convenient for us. The software combines technology with design, editing and routing IC and PCB coordinate Cadence® Allegro® enables advanced analysis of both pre-layout and post-layout provides for users.
The software is designed to examine various scenarios in the initial phases allows accurate design and redesign minimized. This software supports reading and writing directly on the PCB and IC design of Allego’s database. Accurate simulator based on SPICE as well as built-solver for 2d and 3d extracts the user. The software also modeling the transistor-level input and output functions include power-aware IBIS 5.0 support.
Features and Applications Allegro Sigrity:
-Perform a wide range of SI analysis or Signal integrity (signal integrity)
-Early detection of design errors to increase success in the early phases
-Restrictions can be set quickly and accurately apply the basic processes
-Improve product performance through exploration and space solutions
-Evaluation of alternative topologies in infancy
-Production of S parameters of the topology and signal analysis in the form of parameter S
-Tables estimate interference designed to increase productivity
-Was approved after PCB design and IC design directly on boards
-Multiple evaluation and confirmation signals for different paths on silicon boards
Sigrity 2021 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis:
Interconnect Modeling Technology:
-Upgraded interconnect modeling technology addresses latest trends on PCB and IC package design.With signal speeds climbing to 32Gbps and faster, the need to strategically model PCBs and connectors as one structure is now required. The new Cadence® Sigrity™ 3D Workbench, included with the Sigrity PowerSI 3D EM Extraction Option (3DEM), allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB. This way critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure. Updates to the PCB can be automatically back-annotated to the PCB layout tool.
The 3D Workbench offers:
-SI and PI applications
-A familiar 3D look and feel
-Ability to import mechanical structures
-Ability to import electrical databases and merge with mechanical structures
-3D solid modeling (parametric and full featured)
-Simulation of:
-Twisted pair wiring (cables)
-Backplane plus connectors
-Connector modeling (HDMI, SATA, etc.)
-SMA connector on a PCB
Rigid-Flex Support:
Industry-first full Rigid-Flex PCB extraction from a single layout database provides accurate interconnect modeling of both rigid and meshed-ground flex cable zones. The zone information is automatically imported from version 17.2 of Cadence Allegro® technology.
Faster IC Package Modeling:
-IC package modeling of designs with thousands of bumps/balls is now 3X faster and memory consumption has been reduced by 75 percent.
Power Integrity Updates:
-Upgraded power integrity (PI) technology addresses new checking requirements and new usability requirements for PCB front-to-back design flows. Many enhancements have been added, including hierarchical views, quick search, and filtering, comparison tree report, and tool tips.
Allegro PowerTree™ technology:
-The DC analysis technology has been upgraded to support integration with Allegro technology, HTML block-diagram enhancements, and automated add-nodes-on-pads enhancements.
Sigrity PowerDC™ technology:
-The AC analysis technology has added some additional checks that now look at the weighted AC current and checks for equal voltage. New batch-mode “projects” allow these two new workflows as well as others to be setup as a set of batch checks.
Sigrity OptimizePI™ technology:
-Upgraded signal integrity (SI) technology accelerates the time it takes to verify memory interfaces, serial links, and the plethora of other signals on a PCB that can cause a design to fail in the lab. The technology now features workflows and visions that can be used to quickly perform electrical rule checks that find impedance variations and excessive coupling. These checks require no models and can be run by both expert and non-experts in signal integrity.
System Requirements:
OS:Windows 10 (64-bit), Windows 2012 Server (All service packs), Windows 2016 Server (All service packs).
Note:Note: Clarity 3D Solver and Celsius with Hyper-V are not supported on Windows 7.
CPU:Intel® Core™ i7 4.30 GHz or AMD Ryzen™ 7 4.30 GHz with at least 4 cores
RAM:8 GB RAM / 64 GB RAM or higher
Space:50 GB free disk space / 500 GB free disk space SSD is recommended for primary operating system (OS) and simulation working directory
Internet:Microsoft® Internet Explorer® 9.0 or later
Display:1,024 x 768 display resolution with true color (16bit color) / Large monitor (or two) with Full HD resolution or higher
GPU:Dedicated graphics card with 1 GB video memory or higher
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